military and industrial temperature ranges idt54/74fct273t/at/ct fast cmos octal d flip-flop with master reset 1 june 2002 military and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. ? 2002 integrated device technology, inc. dsc-2568/2 features: ? std., a, and c grades ? low input and output leakage 1a (max.) ? cmos power levels ? true ttl input and output compatibility: ?v oh = 3.3v (typ.) ?v ol = 0.3v (typ.) ? high drive outputs (-15ma i oh , 48ma i ol ) ? meets or exceeds jedec standard 18 specifications ? military product compliant to mil-std-883, class b and desc listed (dual marked) ? power off disable outputs permit "live insertion" ? available in the following packages: ? industrial: soic, ssop, qsop ? military: cerdip, lcc functional block diagram idt54/74fct273t/at/ct fast cmos octal d flip-flop with master reset description: the fct273t is an octal d flip-flop built using an advanced dual metal cmos technology. the fct273t has eight edge-triggered d-type flip- flops with individual d inputs and o outputs. the common buffered clock (cp) and master reset ( mr ) inputs load and reset (clear) all flip-flops simultaneously. the register is fully edge-triggered. the state of each d input, one set- up time before the low-to-high clock transition, is transferred to the corre- sponding flip-flop?s o output. all outputs will be forced low independently of clock or data inputs by a low voltage level on the mr input. the device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. d cp q r d d 0 o 0 d cp q r d d 1 o 1 d cp q r d d 2 o 2 d cp q r d d 3 o 3 d cp q r d d 4 o 4 d cp q r d d 5 o 5 d cp q r d d 6 o 6 d cp q r d d 7 o 7 cp mr
military and industrial temperature ranges 2 idt54/74fct273t/at/ct fast cmos octal d flip-flop with master reset pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. output and i/o terminals only. pin names description dx data inputs mr master reset (active low) c p clock pulse input (active rising edge) o x data outputs pin description symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. lcc top view cerdip/ soic/ ssop/ qsop top view function table (1) inputs outputs operating mode mr cp dx ox reset (clear) l x x l load "1" l hh load "0" h ll 2 3 1 16 15 14 11 19 18 20 17 13 12 5 6 7 4 8 9 10 d 1 o 0 d 0 v cc o 1 d 3 o 2 d 2 o 3 gnd o 7 o 6 d 7 d 6 o 5 o 4 d 5 d 4 cp mr 1 2 3 4 5 7 9 6 8 10 11 12 13 14 15 16 17 18 19 20 o 6 d 7 d 6 o 5 d 5 d 0 o 0 o 3 g n d c p o 4 d 4 m r v c c o 7 index d 1 o 1 d 3 o 2 d 2 note: 1. h = high voltage level steady state h = high voltage level one set-up time prior to the low-to-high clock transition l = low voltage level steady state i = low voltage level one set-up time prior to the low-to-high clock transition x = don?t care = low-to-high clock transition
military and industrial temperature ranges idt54/74fct273t/at/ct fast cmos octal d flip-flop with master reset 3 symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (4) v cc = max. v i = 2.7v ? ? 1a i il input low current (4) v cc = max. v i = 0.5v ? ? 1 i i input high current (4) v cc = max., v i = v cc (max.) ? ? 1a v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max., v o = gnd (3) ?60 ?120 ?225 ma v oh output high voltage v cc = min i oh = ?6ma mil 2.4 3.3 ? v in = v ih or v il i oh = ?8ma ind v i oh = ?12ma mil 2 3 ? i oh = ?15ma ind v ol output low voltage v cc = min i ol = 32ma mil ? 0.3 0.5 v v in = v ih or v il i ol = 48ma ind v h input hysteresis ? ? 200 ? mv i cc quiescent power supply current v cc = max. ? 0.01 1 ma v in = gnd or v cc dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 5%; military: t a = ?55c to +125c, v cc = 5.0v 10% notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. the test limit for this parameter is 5a at t a = ?55c.
military and industrial temperature ranges 4 idt54/74fct273t/at/ct fast cmos octal d flip-flop with master reset symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. ? 0.5 2 ma ttl inputs high v in = 3.4v (3) i ccd dynamic power supply v cc = max. v in = v cc ? 0.15 0.25 ma/ current (4) outputs open v in = gnd mhz mr = v cc one input toggling 50% duty cycle i c total power supply current (6) v cc = max. v in = v cc ? 1.5 3.5 ma outputs open v in = gnd f cp = 10mhz 50% duty cycle mr = v cc v in = 3.4v ? 2 5.5 one bit toggling v in = gnd fi = 5mhz 50% duty cycle v cc = max. v in = v cc ? 3.8 7.3 (5) outputs open v in = gnd f cp = 10mhz 50% duty cycle mr = v cc v in = 3.4v ? 6 16.3 (5) eight bits toggling v in = gnd fi = 2.5mhz 50% duty cycle notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input; (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of ? i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp /2+ f i n i ) i cc = quiescent current ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = output frequency n i = number of outputs at f i all currents are in milliamps and all frequencies are in megahertz. power supply characteristics
military and industrial temperature ranges idt54/74fct273t/at/ct fast cmos octal d flip-flop with master reset 5 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 74fct273at 74fct273ct symbol parameter condition (1) min. (2) max. min. (2) max. unit t plh propagation delay c l = 50pf 2 7.2 2 5.8 ns t phl cp to ox r l = 500 ? t plh propagation delay 2 7.2 2 6.1 ns t phl mr to ox t su set-up time high or low 2 ? 2 ? ns dx to cp t h hold time high or low 1.5 ? 1.5 ? ns dx to cp t w cp pulse width high or low 6 ? 6 ? ns t w mr pulse width low 6 ? 6 ? ns t rem recovery time mr to cp 2 ? 2 ? ns switching characteristics over operating range - industrial 54fct273t 54fct273at 54fct273ct symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. unit t plh propagation delay c l = 50pf 2 15 2 8.3 2 6.5 ns t phl cp to ox r l = 500 ? t plh propagation delay 2 15 2 8.3 2 6.8 ns t phl mr to ox t su set-up time high or low 3.5 ? 2 ? 2 ? ns dx to cp t h hold time high or low 2 ? 1.5 ? 1.5 ? ns dx to cp t w cp pulse width high or low 7 ? 6 ? 6 ? ns t w mr pulse width low 7 ? 6 ? 6 ? ns t rem recovery time mr to cp 5 ? 2.5 ? 2.5 ? ns switching characteristics over operating range - military
military and industrial temperature ranges 6 idt54/74fct273t/at/ct fast cmos octal d flip-flop with master reset pulse generator r t d.u.t . v cc v in c l v out 50pf 500 ? 500 ? 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
military and industrial temperature ranges idt54/74fct273t/at/ct fast cmos octal d flip-flop with master reset 7 ordering information idt xx temp. range xxxx device type xx package x process so py q industrial options small outline ic shink small outline package quarter-size small outline package octal d flip-flop with master reset 54 74 ? 55 c to +125 c ? 40 c to +85 c d l military options cerdip leadless chip carrier blank b industrial mil-std-883, class b fct 273t 273at 273ct corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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